diff options
| author | Dinh Nguyen <[email protected]> | 2017-06-08 09:18:39 -0500 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2017-06-19 17:01:55 -0700 |
| commit | b7f8101d6e75fefd22c39624a30c9ed3d7a72463 (patch) | |
| tree | 69bc892406162ff2d5474256ac99eef0038f26e3 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | a925810f6ebb89ef94977c4f499264c8fd199dff (diff) | |
clk: socfpga: Fix the smplsel on Arria10 and Stratix10
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.
Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.
Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions