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authorPratyush Yadav <[email protected]>2020-10-05 21:01:38 +0530
committerVignesh Raghavendra <[email protected]>2020-11-09 19:00:14 +0530
commitad624dfd7bb69a20ff06804ece25bc27200f2ea2 (patch)
tree6c290ae6371fcd55937b53453df3929fcce3714a /tools/perf/util/scripting-engines/trace-event-python.c
parentc3266af101f28e87505c976fad8db96c68f8afe4 (diff)
mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode
Since this flash doesn't have a Profile 1.0 table, the Octal DTR capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D fast read settings. Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency of 200Mhz. The flash supports the soft reset sequence. So, add the flag in the flash's info. Signed-off-by: Pratyush Yadav <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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