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| author | Li Ming <[email protected]> | 2024-08-09 08:27:49 +0000 |
|---|---|---|
| committer | Dave Jiang <[email protected]> | 2024-08-09 15:13:07 -0700 |
| commit | 8c251c5ab1b7cd204231e4ee936bfe078a33f234 (patch) | |
| tree | 6a39c7a55e8ca64dedd86332383ac9a0310bb3dd /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | de9c2c66ad8e787abec7c9d7eff4f8c3cdd28aed (diff) | |
cxl/pci: Get AER capability address from RCRB only for RCH dport
cxl_setup_parent_dport() needs to get RCH dport AER capability address
from RCRB to disable AER interrupt. The function does not check if dport
is RCH dport, it will get a wrong pci_host_bridge structure by dport_dev
in VH case because dport_dev points to a pci device(RP or switch DSP)
rather than a pci host bridge device.
Fixes: f05fd10d138d ("cxl/pci: Add RCH downstream port AER register discovery")
Signed-off-by: Li Ming <[email protected]>
Reviewed-by: Dan Williams <[email protected]>
Reviewed-by: Ira Weiny <[email protected]>
Tested-by: Ira Weiny <[email protected]>
Tested-by: Alison Schofield <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Dave Jiang <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions