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| author | Shubhrajyoti Datta <[email protected]> | 2020-06-17 17:07:26 +0530 |
|---|---|---|
| committer | Bartosz Golaszewski <[email protected]> | 2020-06-24 12:16:57 +0200 |
| commit | 73c612fe2a5f819bc54598b5babc630528bf29d1 (patch) | |
| tree | fba1582ff6c8ebf6e7ac78467595d4b07e88e256 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 26ebdbf8c2e311759d88c0b0cf26126715e932c6 (diff) | |
gpio: zynq: Add pmc gpio support
Add PMC gpio support.
Only bank 0,1, 3 and 4 are connected to the multiplexed Input output
pins. Bank 0 and 1 to mio and bank 3 and 4 to extended multiplexed input
output pins.
Versal devices are the industry's first adaptive compute
acceleration platforms.
https://www.xilinx.com/support/documentation/data_sheets/ds950-versal-overview.pdf
On the Versal platform, we are using two customized GPIO controllers(IP)
which were used in Zynq/ZynqMp platform.
One of them present in the Platform Management Controller(PMC) block and
other in Processing System(PS) block.
In PMC_GPIO only Bank0,1,3 & 4 are enabled and in PS_GPIO only
Bank 0 & 3 are enabled.
You can find more details of GPIO IP in ZynqMP TRM General Purpose
I/O(Chapter-27).
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
Signed-off-by: Shubhrajyoti Datta <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions