diff options
| author | Kan Liang <[email protected]> | 2015-04-21 05:34:41 -0400 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2015-05-08 11:59:41 +0200 |
| commit | 6d374056354a742eed4d0050498101e56e794c4b (patch) | |
| tree | f03f738d250802781de0f3f84fc297e3b7694bf4 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 8b10c5e2b59ef2a80a07ab594a3b4987a4676211 (diff) | |
perf/x86/intel: Fix SLM cache event list
iTLB-load-misses and LLC-load-misses count incorrectly on SLM.
There is no ITLB.MISSES support on SLM. Event PAGE_WALKS.I_SIDE_WALK
should be used to count iTLB-load-misses. This event counts when an
instruction (I) page walk is completed or started. Since a page walk
implies a TLB miss, the number of TLB misses can be counted by counting
the number of pagewalks.
DMND_DATA_RD counts both demand and DCU prefetch data reads. However,
LLC-load-misses should only count demand reads. There is no way to not
include prefetches with a single counter on SLM. So the LLC-load-misses
support should be removed on SLM.
Signed-off-by: Kan Liang <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: H. Peter Anvin <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions