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authorLauri Kasanen <[email protected]>2014-04-02 20:03:57 +0300
committerDave Airlie <[email protected]>2014-04-04 09:28:14 +1000
commit62347f9e0f81d50e9b0923ec8a192f60ab7a1801 (patch)
treeb7d6db268abfe08ff52742a47902474877bfa0a4 /tools/perf/util/scripting-engines/trace-event-python.c
parent2614dc66837c2a6fd0e14e3f8e72343782c8b784 (diff)
drm: Add support for two-ended allocation, v3
Clients like i915 need to segregate cache domains within the GTT which can lead to small amounts of fragmentation. By allocating the uncached buffers from the bottom and the cacheable buffers from the top, we can reduce the amount of wasted space and also optimize allocation of the mappable portion of the GTT to only those buffers that require CPU access through the GTT. For other drivers, allocating small bos from one end and large ones from the other helps improve the quality of fragmentation. Based on drm_mm work by Chris Wilson. v3: Changed to use a TTM placement flag v2: Updated kerneldoc Cc: Chris Wilson <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Christian König <[email protected]> Signed-off-by: Lauri Kasanen <[email protected]> Signed-off-by: David Airlie <[email protected]>
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