diff options
| author | Eugen Hristev <[email protected]> | 2022-06-30 12:09:26 +0300 |
|---|---|---|
| committer | Ulf Hansson <[email protected]> | 2022-07-12 12:42:37 +0200 |
| commit | 5987e6ded29d52e42fc7b06aa575c60a25eee38e (patch) | |
| tree | 87f84eadec10e73206874db63c9227196bace21a /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | e427266460826bea21b70f9b2bb29decfb2c2620 (diff) | |
mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R
In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
register.
This can lead to accidental erase of certain bits in this register.
Avoid this by doing a read-modify-write operation.
Fixes: d0918764c17b ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
Signed-off-by: Eugen Hristev <[email protected]>
Tested-by: Karl Olsen <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ulf Hansson <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions