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authorMax Filippov <[email protected]>2014-12-26 20:19:38 +0300
committerMark Brown <[email protected]>2015-01-08 19:52:11 +0000
commit57b7068de5d0cca8ac6e21085b843c1bbd49d3f4 (patch)
tree7f967c6eada43604a8dd30e88141f70bbc4e91b5 /tools/perf/util/scripting-engines/trace-event-python.c
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
ASoC: add xtensa xtfpga I2S interface and platform
XTFPGA boards provides an audio subsystem that consists of TI CDCE706 clock synthesizer, I2S transmitter and TLV320AIC23 audio codec. I2S transmitter has MMIO-based interface that resembles that of the OpenCores I2S transmitter. I2S transmitter is always a master on I2S bus. There's no specialized audio DMA, sample data are transferred to I2S transmitter FIFO by CPU through memory-mapped queue interface. Signed-off-by: Max Filippov <[email protected]> Signed-off-by: Mark Brown <[email protected]>
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