diff options
| author | Kisoo Yu <[email protected]> | 2012-04-24 14:54:15 -0700 |
|---|---|---|
| committer | Kukjin Kim <[email protected]> | 2012-05-16 07:03:41 +0900 |
| commit | 57b317f912b3f4b05c834818c73d7c8ea22642f7 (patch) | |
| tree | 9963b419762b3bbe9a30544c9543edb199df5cde /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | f10590c9836c9fc595d1dafff965b280029d4f16 (diff) | |
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.
Signed-off-by: Kisoo Yu <[email protected]>
Signed-off-by: Thomas Abraham <[email protected]>
[[email protected]: moved common pll stuff into s5p-clock.c]
Signed-off-by: Kukjin Kim <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions