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| author | Rajendra Nayak <[email protected]> | 2012-05-07 23:55:21 -0600 |
|---|---|---|
| committer | Paul Walmsley <[email protected]> | 2012-05-07 23:55:21 -0600 |
| commit | 4e68f5a79da5b595fc40ceff5ebcfa3e6637bf37 (patch) | |
| tree | 1756942d86be26b7790a7fb825e816708f5b197d /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 96566043b19ae76d3828ce75cbf28dc6d0bcaaf1 (diff) | |
ARM: OMAP3: Fix CM register bit masks
The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide. Fix the MASK definition accordingly.
Signed-off-by: Rajendra Nayak <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions