diff options
| author | Gabor Juhos <[email protected]> | 2012-03-14 10:45:24 +0100 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2012-05-15 17:49:08 +0200 |
| commit | 4dbcbdf8135def8f704b130305721bdd42a8078b (patch) | |
| tree | f6b8dec7781a7ece62f55af354ba6f5e49d37fdb /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 5b5b544ed32a1b6ad4d7706fcee530eb67670e71 (diff) | |
MIPS: ath79: rework IP2/IP3 interrupt handling
The current implementation assumes that flushing the
DDR writeback buffer is required for IP2/IP3 interrupts,
however this is not true for all SoCs.
Use SoC specific IP2/IP3 handlers instead of flushing
the buffers in the dispatcher code.
Signed-off-by: Gabor Juhos <[email protected]>
Acked-by: Luis R. Rodriguez <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/3509/
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions