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authorDinh Nguyen <[email protected]>2014-09-04 16:45:56 -0500
committerDinh Nguyen <[email protected]>2014-11-20 23:08:42 -0600
commit475dc86d08de4af61b6e8524bbcdbf8d675cb4fa (patch)
tree499b98442fdd1c59461e1d10f057f2836fa25ba8 /tools/perf/util/scripting-engines/trace-event-python.c
parentc1ad85d77224b91448761a3f0ab0d14459c7bb44 (diff)
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
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