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authorOlof Johansson <[email protected]>2019-11-08 10:27:55 -0800
committerOlof Johansson <[email protected]>2019-11-08 10:27:57 -0800
commit44a39847787b022c9f64b48b41c9d2f9dcd815f4 (patch)
tree197fdf07ebab080177683febdf2126d56ff77f1e /tools/perf/util/scripting-engines/trace-event-python.c
parentd4b0c97a80891d5fb8d73230730f28a42f16fe28 (diff)
parentaf3f1afac38d34083faad852172d0ec82749c046 (diff)
Merge tag 'zynqmp-soc-for-v5.5' of https://github.com/Xilinx/linux-xlnx into arm/drivers
arm64: soc: Xilinx SoC changes for v5.5 - Extend firmware interface to cover Versal chip * tag 'zynqmp-soc-for-v5.5' of https://github.com/Xilinx/linux-xlnx: firmware: xilinx: Add support for versal soc dt-bindings: firmware: Add bindings for Versal firmware soc: xilinx: Set CAP_UNUSABLE requirement for versal while powering down domain Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
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