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authorAlexandru Ardelean <[email protected]>2021-02-01 17:12:42 +0200
committerStephen Boyd <[email protected]>2021-02-08 18:13:12 -0800
commit324a810583ffec3e5c6e7e35bc202904d362e71b (patch)
tree9c509095b1b58009fd865b79d722edbb7e004233 /tools/perf/util/scripting-engines/trace-event-python.c
parent5c8fe583cce542aa0b84adc939ce85293de36e5e (diff)
clk: axi-clkgen: replace ARCH dependencies with driver deps
The intent is to be able to run this driver to access the IP core in setups where FPGA board is also connected via a PCIe bus. In such cases the number of combinations explodes, where the host system can be an x86 with Xilinx Zynq/ZynqMP/Microblaze board connected via PCIe. Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe. To accommodate for these cases, this change removes the limitation for this driver to be compilable only on Zynq/Microblaze architectures. And adds dependencies on the mechanisms required by the driver to work (OF and HAS_IOMEM). Signed-off-by: Dragos Bogdan <[email protected]> Signed-off-by: Alexandru Ardelean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Michal Simek <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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