diff options
| author | Will Deacon <[email protected]> | 2011-10-03 18:30:53 +0100 |
|---|---|---|
| committer | Russell King <[email protected]> | 2011-10-15 11:04:22 +0100 |
| commit | 29a541f6c1f6e4a85628bb86071b9e72c9f8be2c (patch) | |
| tree | 9f132fd63c08266901f3427d624891ac7e2da7b7 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 002ea9eefec98dada56fd5f8e432a4e8570c2a26 (diff) | |
ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
Using COHERENT_LINE_{MISS,HIT} for cache misses and references
respectively is completely wrong. Instead, use the L1D events which
are a better and more useful approximation despite ignoring instruction
traffic.
Reported-by: Alasdair Grant <[email protected]>
Reported-by: Matt Horsnell <[email protected]>
Reported-by: Michael Williams <[email protected]>
Cc: [email protected]
Cc: Jean Pihet <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions