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author | Harry Pan <[email protected]> | 2018-03-09 20:15:48 +0800 |
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committer | Ingo Molnar <[email protected]> | 2018-03-31 11:28:36 +0200 |
commit | 1159e09476536250c2a0173d4298d15114df7a89 (patch) | |
tree | c7602afbb5f98b270f071b87e695ffd8d3218911 /tools/perf/util/scripting-engines/trace-event-python.c | |
parent | 490d03e83da2a5e9d7db84b1ec30a9c95415787e (diff) |
perf/x86/intel: Enable C-state residency events for Cannon Lake
Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10
state residency counters, this patch enables those counters.
( The MSR information is based on Intel Software Developers' Manual,
Vol. 4, Order No. 335592. )
Tested-by: Puthikorn Voravootivat <[email protected]>
Signed-off-by: Harry Pan <[email protected]>
Reviewed-by: Benson Leung <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: [email protected]
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Stephane Eranian <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Vince Weaver <[email protected]>
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions