diff options
| author | Takeshi Kihara <[email protected]> | 2017-07-28 20:41:13 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2017-08-16 14:26:24 +0200 |
| commit | 50d83156e84ee5112fa07a0033eef4e58110709d (patch) | |
| tree | 8ff1ad161f13baf2b60e6e5ec7080d6d7edb02e3 /tools/perf/util/c++/clang.cpp | |
| parent | 933ddbe5f52fbd6bdb03b976b7b1b80230b3b9a9 (diff) | |
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24].
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.
Fixes: 0b0ffc96dbe30fa9 ("pinctrl: sh-pfc: Initial R8A7795 PFC support")
Signed-off-by: Takeshi Kihara <[email protected]>
Signed-off-by: Yoshihiro Kaneko <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/util/c++/clang.cpp')
0 files changed, 0 insertions, 0 deletions