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authorKahola, Mika <[email protected]>2017-06-09 15:26:15 -0700
committerRodrigo Vivi <[email protected]>2017-06-12 09:46:30 -0700
commit1fa62e1b76d6fb4e353f6d7e3ec22e6d07e0a489 (patch)
tree2e5291ee73fd6d03098b89143e03dd25cff3bf97 /tools/perf/util/c++/clang.cpp
parentff15947e0f02ceccfffa8f342472765404d161b6 (diff)
drm/i915/cnl: Enable wrpll computation for CNL
Enable wrpll computation for Cannonlake platform to support pll's required for HDMI output. The patch contains the following features - compute Cannonlake port clock programming dividers P, Q, and K. - compute PLL parameters for Cannonlake. These parameters set the values on DPLL registers. - find the register values to program wrpll for Cannonlake. The reference clock can be either 19.2MHz or 24MHz. v2: rebase v3: squash wrpll patches into one (Rodrigo) v4: switch order of getting even dividers (Paulo) update divider register values for PDiv and KDiv (Paulo) update wrpll computation algorithm (Paulo) v5: Remove ref clock division by 1000. (Rodrigo) v6: Rodrigo rebasing on top of latest code. Signed-off-by: Kahola, Mika <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
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