diff options
| author | Koji Matsuoka <[email protected]> | 2016-05-16 11:28:15 +0900 |
|---|---|---|
| committer | Laurent Pinchart <[email protected]> | 2016-11-15 01:44:50 +0200 |
| commit | fd1adef3bff0663c5ac31b45bc4a05fafd43d19b (patch) | |
| tree | 4e8895caca0db0d50f0551e4c134a6ba1cc99f90 /tools/perf/scripts/python | |
| parent | 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 (diff) | |
drm: rcar-du: Fix H/V sync signal polarity configuration
The VSL and HSL bits in the DSMR register set the corresponding
horizontal and vertical sync signal polarity to active high. The code
got it the wrong way around, fix it.
Signed-off-by: Koji Matsuoka <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions