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authorJonathan Cameron <[email protected]>2022-05-08 18:57:09 +0100
committerJonathan Cameron <[email protected]>2022-06-14 11:53:19 +0100
commitfaa05ecb1349070d874810e161b653c2220e0006 (patch)
tree7c5a356409548e00ad1abbe57d59e9071abf9777 /tools/perf/scripts/python
parent37882314d3bdc2ae775ebb9fa8ed7a94cd1aad61 (diff)
iio: resolver: ad2s90: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes tag is probably not where the issue was first introduced, but is likely to be far beyond the point where anyone considers backporting this fix. Fixes: 58f08b0af857 ("staging:iio:resolver:ad2s90 general cleanup") Signed-off-by: Jonathan Cameron <[email protected]> Acked-by: Nuno Sá <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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