diff options
| author | Suzuki K Poulose <[email protected]> | 2017-08-02 10:22:16 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2017-08-28 16:05:49 +0200 |
| commit | f2e931a2deab1ab426085f0357285410644f2945 (patch) | |
| tree | b61f1b5849575d47e3cb71f3d7bb9e0ab99ef611 /tools/perf/scripts/python | |
| parent | ebab6a7db2c599b5c29d033f3a20f86016d9a9b8 (diff) | |
coresight tmc: Support for save-restore in ETR
The Coresight SoC 600 TMC ETR supports save-restore feature,
where the values of the RRP/RWP and STS.Full are retained
when it leaves the Disabled state. Hence, we must program the
RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP
to the base address of the buffer and clear the STS.Full register.
This can be later exploited for proper save-restore of ETR
trace contexts (e.g, perf).
Cc: Mathieu Poirier <[email protected]>
Signed-off-by: Suzuki K Poulose <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions