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| author | Reinette Chatre <reinette.chatre@intel.com> | 2018-06-22 15:42:20 -0700 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-06-23 13:03:49 +0200 |
| commit | f2a177292bd052ce12ac453d2ceeb083fe07718a (patch) | |
| tree | 005de372bbef68b4de7c56a1ed0943a0c2d25d19 /tools/perf/scripts/python | |
| parent | 72d505056604a305a4fcd8b268d2f6e979e17023 (diff) | |
x86/intel_rdt: Discover supported platforms via prefetch disable bits
Knowing the model specific prefetch disable bits is required to support
cache pseudo-locking because the hardware prefetchers need to be disabled
when the kernel memory is pseudo-locked to cache. We add these bits only
for platforms known to support cache pseudo-locking.
When the user requests locksetup mode to be entered it will fail if the
prefetch disabling bits are not known for the platform.
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: fenghua.yu@intel.com
Cc: tony.luck@intel.com
Cc: vikas.shivappa@linux.intel.com
Cc: gavin.hindman@intel.com
Cc: jithu.joseph@intel.com
Cc: dave.hansen@intel.com
Cc: hpa@zytor.com
Link: https://lkml.kernel.org/r/3eef559aa9fd693a104ff99ff909cfee450c1695.1529706536.git.reinette.chatre@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions