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authorMika Kuoppala <[email protected]>2020-05-06 17:47:31 +0300
committerChris Wilson <[email protected]>2020-05-07 07:44:40 +0100
commitf02ac414ba9497d1887b1de7fe69954284f157ac (patch)
tree8c26324826f1e9eecb0f3cd6218e444a2f02da4e /tools/perf/scripts/python
parent24fe5f2ab2478053d50a3bc629ada895903a5cbc (diff)
Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
This reverts commit 62037ffff229b7d94f1db5ef8d2e2ec819832ef3. L3 ro cache invalidation is part of the dword0 of pipe control. Also it is not relevant to this gen. Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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