diff options
| author | Sai Prakash Ranjan <[email protected]> | 2020-08-18 20:25:14 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2020-08-30 17:24:30 +0000 |
| commit | efe788361f72914017515223414d3f20abe4b403 (patch) | |
| tree | 1897a5b88262425f08818a4ed5b0527abe608060 /tools/perf/scripts/python | |
| parent | 0e6aa9db44e7bbba7efeff3b4fc1fa61bab318c2 (diff) | |
arm64: dts: qcom: sc7180: Fix the LLCC base register size
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.
Reviewed-by: Douglas Anderson <[email protected]>
Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions