diff options
| author | Lad Prabhakar <[email protected]> | 2024-07-30 13:24:33 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2024-08-23 15:43:26 +0200 |
| commit | ec9532628eb9d82282b8e52fd9c4a3800d87feec (patch) | |
| tree | d2332158babcc67712f78e7e55888124a82d6e25 /tools/perf/scripts/python | |
| parent | bdfa062d14b22e36207c219206b2bf770d5363b3 (diff) | |
arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes
The RZ/G3S SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB
for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU.
Despite the RZ/G3S SoC being single-core, it has two instances of GICR.
Fixes: e20396d65b959 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC")
Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions