diff options
| author | José Roberto de Souza <[email protected]> | 2020-02-27 14:00:51 -0800 |
|---|---|---|
| committer | José Roberto de Souza <[email protected]> | 2020-03-02 12:00:39 -0800 |
| commit | ec1e12645ff3987f660ef9dc21c9db548b43ee9b (patch) | |
| tree | b7adb6d88d2693d1e9702333610e1686d5333176 /tools/perf/scripts/python | |
| parent | ccc495fd7ac3815702378712bccc1cbfc7852b58 (diff) | |
drm/i915/tgl: Implement Wa_1409804808
This workaround the CS not done issue on PIPE_CONTROL.
v2:
- replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits
- shortened the name of the new bit
BSpec: 52890
BSpec: 46218
Cc: Matt Roper <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Signed-off-by: José Roberto de Souza <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions