diff options
| author | Ben Skeggs <[email protected]> | 2012-09-27 08:55:53 +1000 |
|---|---|---|
| committer | Ben Skeggs <[email protected]> | 2012-10-03 13:13:17 +1000 |
| commit | e5f186c4f9812eccbc291da6dfe8b15da546f961 (patch) | |
| tree | 84e667ebbe00bd91e10cff16defaad95b38d85a9 /tools/perf/scripts/python | |
| parent | 8a57d279d6e1bf19d2d2e54f51d4f40c46c7d1a8 (diff) | |
drm/nv44/vm: fix and enable use of "real" pciegart
Something seems to be missing in regards to flushing specific ranges of
the TLB. For the moment, flushing the entire thing seems to make it
work alright.
Should give 39-bit DMA addressing on the relevant chipsets.
v2: allocate contig 16KiB for dummy pages, reported by mwk on irc
Signed-off-by: Ben Skeggs <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions