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authorNicholas Kazlauskas <[email protected]>2020-07-09 16:21:37 -0400
committerAlex Deucher <[email protected]>2020-07-14 14:38:17 -0400
commite2f60fd8ba6199e6d1f3191239613834d5fcf5ad (patch)
tree8263becfe463c3ca90fea1f55415aa23d75a2022 /tools/perf/scripts/python
parent4462282a7253e3663790f8ab092a4107d905bd76 (diff)
drm/amd/display: Add missing DCN30 registers and fields for OTG_CRC_CNTL2
[Why] When enabling the debugfs for CRC capture we hit assertions caused by register address and field masks and shifts missing. [How] We want these registers programmed, so add in the SRI/SF entries for this register. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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