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| author | Biju Das <[email protected]> | 2022-04-02 08:46:25 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-04-13 12:30:19 +0200 |
| commit | e11f804afc12e1c622f0a6f966fafd05b7022f8a (patch) | |
| tree | 6f92a6c5cb53e2aa408007a90bd919f856f886d1 /tools/perf/scripts/python | |
| parent | f201eb84450f98decb1834e73409bb2271441dd7 (diff) | |
clk: renesas: r9a07g043: Add GbEthernet clock/reset
Add ETH{0,1} clock/reset entries to CPG driver.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions