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authorAaron Brice <[email protected]>2016-10-06 15:13:04 -0700
committerGreg Kroah-Hartman <[email protected]>2016-10-27 16:41:56 +0200
commitd704b2d32c39c256dea659e142a31b875a13c63b (patch)
treee104411d0b6a56d00ed2f6a8b274ce95292e5d66 /tools/perf/scripts/python
parentf00a7c57569db04633818bc5e0c0e35d62733b02 (diff)
tty: serial: fsl_lpuart: Fix Tx DMA edge case
In the case where head == 0 on the circular buffer, there should be one DMA buffer, not two. The second zero-length buffer would break the lpuart driver, transfer would never complete. Signed-off-by: Aaron Brice <[email protected]> Acked-by: Stefan Agner <[email protected]> Tested-by: Stefan Agner <[email protected]> Tested-by: Bhuvanchandra DV <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
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