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authorStefan Agner <[email protected]>2016-07-19 13:13:05 +0530
committerGreg Kroah-Hartman <[email protected]>2016-08-31 15:48:28 +0200
commitd68827c62a105eec547945daedf4d1d3e283717d (patch)
treeca79c531d0d11f14ab1c04e0816dd562a2169ece /tools/perf/scripts/python
parentd6b0d2f243fef6cb87f5338bf06c2330175f106f (diff)
tty: serial: fsl_lpuart: fix clearing of receive flag
Commit 8e4934c6d6c6 ("tty: serial: fsl_lpuart: clear receive flag on FIFO flush") implemented clearing of the receive flag by reading the status register only. It turned out that even though we flush the FIFO afterwards, a explicit read of the data register is still required. This leads to a FIFO underrun. To avoid this, follow the advice in the overrun "Operation section": Unconditionally clear RXUF after using RXFLUSH. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Bhuvanchandra DV <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
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