diff options
| author | Suzuki K Poulose <[email protected]> | 2017-08-02 10:22:14 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2017-08-28 16:05:49 +0200 |
| commit | cd407abd5efd6f36b6372d615fbab486936e90f4 (patch) | |
| tree | 1f2f04f34ef21401c540b622c7dfec93e424d655 /tools/perf/scripts/python | |
| parent | ff11f5bc5a42f2cfc9705481eedf1b4d470ade2c (diff) | |
coresight tmc etr: Cleanup AXICTL register handling
This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.
Cc: Mathieu Poirier <[email protected]>
Signed-off-by: Suzuki K Poulose <[email protected]>
Signed-off-by: Mathieu Poirier <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions