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authorMaxim Levitsky <[email protected]>2020-09-21 13:38:05 +0300
committerPaolo Bonzini <[email protected]>2020-09-28 07:57:18 -0400
commitcc5b54dd58d0420c1b1f1e9b29f53327076e9355 (patch)
treedd66708ba273fb82968121926b82471059d6e1bc /tools/perf/scripts/python
parent871c433bae565306cfc3a1a386bf7328bc9d31cb (diff)
KVM: x86: fix MSR_IA32_TSC read for nested migration
MSR reads/writes should always access the L1 state, since the (nested) hypervisor should intercept all the msrs it wants to adjust, and these that it doesn't should be read by the guest as if the host had read it. However IA32_TSC is an exception. Even when not intercepted, guest still reads the value + TSC offset. The write however does not take any TSC offset into account. This is documented in Intel's SDM and seems also to happen on AMD as well. This creates a problem when userspace wants to read the IA32_TSC value and then write it. (e.g for migration) In this case it reads L2 value but write is interpreted as an L1 value. To fix this make the userspace initiated reads of IA32_TSC return L1 value as well. Huge thanks to Dave Gilbert for helping me understand this very confusing semantic of MSR writes. Signed-off-by: Maxim Levitsky <[email protected]> Message-Id: <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
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