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authorMatt Carlson <[email protected]>2009-11-13 13:03:40 +0000
committerDavid S. Miller <[email protected]>2009-11-15 22:14:43 -0800
commitcbf9ca6cf8304beb640a948709c4672bc1d5a55f (patch)
treef1941d408d9db7eb4524fc6423de19f3ef16c342 /tools/perf/scripts/python
parent615774fe598f8ee971a8dfeb1f2ec4211241c433 (diff)
tg3: Allow DMAs to cross cacheline boundaries
By default, the 5717 (and future chips) break up PCIe DMA packets across cacheline boundaries. This isn't necessary on x86. This patch selectively loosens the restriction. Signed-off-by: Matt Carlson <[email protected]> Reviewed-by: Michael Chan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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