serial: sirf: use uart_port's fifosize for fifo related operation

In SiRF platform, there are different fifo size of uart and usp,
with the fifosize configuration changes in different chips, we
can not use port line to decide how to check FIFO full,empty and
level.

There is a direct mapping between FIFO HW register layout with
fifo size, so move to use fifosize as the input to check fifo
status.

Signed-off-by: Qipan Li <[email protected]>
Signed-off-by: Barry Song <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

0 files changed, 0 insertions, 0 deletions