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| author | Sherry Sun <sherry.sun@nxp.com> | 2022-04-27 09:51:36 +0800 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-07-22 14:31:30 +0200 |
| commit | be76ceaf03bc04e74be5e28f608316b73c2b04ad (patch) | |
| tree | 5a9fc74eb571e14395f6e325812fd588852c1404 /tools/perf/scripts/python | |
| parent | ff6992735ade75aae3e35d16b17da1008d753d28 (diff) | |
EDAC/synopsys: Use the correct register to disable the error interrupt on v3 hw
v3.x Synopsys EDAC DDR doesn't have the QOS Interrupt register. Use the
ECC Clear Register to disable the error interrupts instead.
Fixes: f7824ded4149 ("EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR")
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220427015137.8406-2-sherry.sun@nxp.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions