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| author | Vishnu Patekar <[email protected]> | 2016-01-31 09:20:55 +0800 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2016-02-02 14:14:24 +0100 |
| commit | be338e4c589935a95f09022566ec6c511c07bb8c (patch) | |
| tree | 0217cf45c688d55cc03e712a28916ac4a2636ab2 /tools/perf/scripts/python | |
| parent | 2d6f5f0cf6bfb17b8f0102cabe0665098ce0a865 (diff) | |
clk: sunxi: add bus gates for A83T
A83T has similar bus gates that of H3, including single gating register has
different clock parent.
As per H3 and A83T datasheet, usbhost is under AHB2.
However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits 29, 30, 31(ohci0,1,2) => AHB2 for H3.
until, this confusion is cleared keep it H3 way.
Signed-off-by: Vishnu Patekar <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions