diff options
| author | Paulo Zanoni <[email protected]> | 2012-10-23 18:30:05 -0200 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2012-10-26 10:24:50 +0200 |
| commit | b8fc2f6a18052194c486b407765a4f5e4dca692d (patch) | |
| tree | 1a1db94b0ffb90cd25d65ae8e419acbd6673e8c7 /tools/perf/scripts/python | |
| parent | e6f0bfc4fb963da9e945ebc6330db9a4d756ba78 (diff) | |
drm/i915: set the correct eDP aux channel clock divider on DDI
The cdclk frequency is not always the same, so the value here should
be adjusted to match it.
Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.
Signed-off-by: Paulo Zanoni <[email protected]>
Reviewed-by: Rodrigo Vivi <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions