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authorChris Wilson <[email protected]>2019-11-18 18:49:33 +0000
committerChris Wilson <[email protected]>2019-11-19 10:11:29 +0000
commitb6422694c5853f7a4faf00431c9d7b5368138152 (patch)
treed629bfa2285133c24ab29e6c81ae43e5a6f1a5f3 /tools/perf/scripts/python
parentd147483884ed08ee6bb618ef610ee0329a27fda7 (diff)
drm/i915/gt: Only wait for register chipset flush if active
Only serialise with the chipset using an mmio if the chipset is currently active. We expect that any writes into the chipset range will simply be forgotten until it wakes up. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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