drm/i915: BXT DDI PHY sequence BUN

According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
checked to ensure that the register is in accessible state.
Also, based on a BSpec update, changing the timeout value to
check iphypwrgood, from 10ms to wait for up to 100us.

v2: [Ville] use wait_for_us instead of the atomic call.
v3: [Jani/Imre] read register only once

Signed-off-by: Vandana Kannan <[email protected]>
Reported-by: Philippe Lecluse <[email protected]>
Cc: Deak, Imre <[email protected]>
Cc: Nikula, Jani <[email protected]>
Acked-by: Jani Nikula <[email protected]>
Reviewed-by: Imre Deak <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]

0 files changed, 0 insertions, 0 deletions