CLK: Pistachio: Register core clocks

Register the clocks generated by the core clock controller.
This includes the 7 PLLs and clocks for the CPU, RPU co-processor,
audio, WiFi, bluetooth, and several other peripherals.

The MIPS and PERIPH_SYS clocks must remain enabled at all times.

Signed-off-by: Damien Horsley <[email protected]>
Signed-off-by: Andrew Bresticker <[email protected]>
Cc: Mike Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Ezequiel Garcia <[email protected]>
Cc: James Hartley <[email protected]>
Cc: James Hogan <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9317/
Signed-off-by: Ralf Baechle <[email protected]>

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