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authorAndrew Davis <[email protected]>2024-08-01 13:12:31 -0500
committerNishanth Menon <[email protected]>2024-08-28 12:14:06 -0500
commit9f3814a7c06b7c7296cf8c1622078ad71820454b (patch)
treed41bfcdeebe8f2ce5f5ec19b2de96a975b8211a7 /tools/perf/scripts/python
parent182a862560097dec7adf774af58076984cd6c1ed (diff)
arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveout locations
The DMA carveout for the C6x core 0 is at 0xa6000000 and core 1 is at 0xa7000000. These are reversed in DT. While both C6x can access either region, so this is not normally a problem, but if we start restricting the memory each core can access (such as with firewalls) the cores accessing the regions for the wrong core will not work. Fix this here. Fixes: f46d16cf5b43 ("arm64: dts: ti: k3-j721e-sk: Add DDR carveout memory nodes") Signed-off-by: Andrew Davis <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nishanth Menon <[email protected]>
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