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authorGeert Uytterhoeven <[email protected]>2022-03-29 11:44:26 +0200
committerGeert Uytterhoeven <[email protected]>2022-04-11 12:13:13 +0200
commit9d18f81b35355f63a39b04869d0a013194925d1a (patch)
tree356aa275e43183384d081204a83f2feda3ccd902 /tools/perf/scripts/python
parent2a214607e4a335f9ebfb08ae3bf7f2c905a0c9c9 (diff)
clk: renesas: r8a77995: Add RPC clocks
Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car E3, but uses a different pre-divider for the PLL0 parent. Add a new macro to describe it, reusing the existing clock type for R-Car E3. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be
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