diff options
| author | Jesse Barnes <[email protected]> | 2012-10-26 09:42:42 -0700 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2012-11-11 23:51:36 +0100 |
| commit | 9a28977181724ebbd9bdc45291cf29da55a729ee (patch) | |
| tree | d83f779436fcaab0b445c64ee50252269ba6b211 /tools/perf/scripts/python | |
| parent | 12f3382bc0262e981a2e58aca900cbbdbbe66825 (diff) | |
drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3
So store into the scratch space of the HWS to make sure the invalidate
occurs.
v2: use GTT address space for store, clean up #defines (Chris)
v3: use correct #define in blt ring flush (Chris)
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Antti Koskipää <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions