diff options
| author | Wayne Lin <[email protected]> | 2021-03-10 23:40:01 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-07-20 16:04:11 -0400 |
| commit | 8a9899c95d1cd709d441960ca325c6c8184978bb (patch) | |
| tree | f49614baa55169ec3df6e9128758d0876dd74a5b /tools/perf/scripts/python | |
| parent | 615dc75fa6a7fc6cf029b01cdfc9d4b78919e71c (diff) | |
drm/amd/display: Support vertical interrupt 0 for all dcn ASIC
[Why]
When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try
to register vertical interrupt 0 for specific task.
Currently, only dcn10 have defined relevant info for vertical interrupt
0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will
get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and
cause pointer errors.
[How]
Add support of vertical interrupt 0 for all dcn ASIC.
Tested-by: Daniel Wheeler <[email protected]>
Acked-by: Alan Liu <[email protected]>
Signed-off-by: Wayne Lin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions