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| author | Kishon Vijay Abraham I <[email protected]> | 2024-06-28 13:45:29 +0200 |
|---|---|---|
| committer | Krzysztof Wilczyński <[email protected]> | 2024-06-28 21:23:59 +0000 |
| commit | 86f271f22bbb6391410a07e08d6ca3757fda01fa (patch) | |
| tree | 20ef8bdc9db19c6536ec2f4608c8399f582666f2 /tools/perf/scripts/python | |
| parent | a231707a91f323af1e5d9f1722055ec2fc1c7775 (diff) | |
PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
(SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
the bus may corrupt the packet payload and the corrupt data may
cause associated applications or the processor to hang.
The workaround for Errata #i2037 is to limit the maximum read
request size and maximum payload size to 128 bytes. Add workaround
for Errata #i2037 here.
The errata and workaround is applicable only to AM65x SR 1.0 and
later versions of the silicon will have this fixed.
[1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf
Link: https://lore.kernel.org/linux-pci/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Achal Verma <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Reviewed-by: Siddharth Vadapalli <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions