diff options
| author | Sakari Ailus <[email protected]> | 2020-07-07 15:24:09 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2020-12-07 15:50:18 +0100 |
| commit | 82ab97c8c77629c4945de24c722cd4955cf70ef2 (patch) | |
| tree | 08f3f5a16173f86a6c005fd7b9678746194d01de /tools/perf/scripts/python | |
| parent | c64cf71d10c36513071ca538f59e4c38eb25ae55 (diff) | |
media: ccs-pll: Fix check for PLL multiplier upper bound
The additional multiplier (for higher VT timing) of the PLL multiplier was
checked against the upper limit but the result was rounded up, possibly
producing too high additional multiplier. Round down instead to keep
within hardware limits.
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions