diff options
| author | Daniel Glöckner <[email protected]> | 2009-04-06 11:50:22 +0200 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2009-04-06 11:18:39 +0100 |
| commit | 80fbe6ac9b47cbc11e174a9bf853834dc281da35 (patch) | |
| tree | 1ad5a6dfdf219fd8e8ce3e0a0ec0be26b11d96a7 /tools/perf/scripts/python | |
| parent | 2b7dbbe0c9491e62b50978d1615193bec33a8291 (diff) | |
ASoC: correct s6000 I2S clock polarity
According to the data sheet data is clocked out on the falling edge
and latched on the rising edge of the bit clock. While the left sample
is transmitted the word clock line is low.
Signed-off-by: Daniel Glöckner <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions