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authorOak Zeng <[email protected]>2021-01-22 21:51:39 -0600
committerAlex Deucher <[email protected]>2021-03-23 22:59:02 -0400
commit79194dacb26a1b31c6d3259144c371795612ce75 (patch)
tree5da30251cd6c5aaf9eabf05f58d284f8b140dcd4 /tools/perf/scripts/python
parentf4ec3e5039e58b85aab486af6a9c3e5d60cf8be0 (diff)
drm/amdgpu: Fix GART page table s-bit
For the new 2-level GART table, the last PDE0 points to PTB. Since PTB is in vram and right now we are runing under s=0 mode (vram is treated as FB carveout), so the s bit of this PDE0 should be set to 0. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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