MIPS: CM, CPC: Ensure core-other GCRs reflect the correct core

Ensure the update to which core the core-other GCR regions reflect has
taken place before any core-other GCRs are accessed by placing a memory
barrier (sync instruction) between the write to the core-other registers
and any such GCR accesses.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Bjorn Helgaas <[email protected]>
Cc: [email protected]
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/11209/
Signed-off-by: Ralf Baechle <[email protected]>

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